Semiconductor raised source-drain structure

ABSTRACT

A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] (Not Applicable)

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

[0002] (Not Applicable)

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention is directed generally to a semiconductorraised source-drain structure and, more particularly, to a semiconductorraised source-drain structure with gate side gaps and pocket junctions.

[0005] 2. Description of the Background

[0006] Raised source and drains have been demonstrated in submicronsemiconductor devices. In contrast to conventional source and drains,raised source and drains are vertical structures formed on top of thesubstrate instead of implanted structures in the substrate surface. Thinfilm structures are typically inserted between the sidewalls of the gateand the top regions of the raised source and drains to isolate the gatefrom the source and drains. Such an isolation arrangement, however, cancause excessive capacitive loading from gate to source and drain.

[0007] Devices incorporating raised source and drains typically includeimplanted n− regions under the source and drain regions to createconductive channels between the gate and the source and drains. Suchchannels do not have good drive and punchthrough capabilities. Also, itis difficult to implant the conductive channels after the polysiliconpattern defining the source and drain structures.

[0008] Thus, there is a need for a semiconductor device with raisedsource and drains that has improved series resistance, good IDS currentdrive, improved punchthrough leakage, and reduced sidewall capacitancethat can be fabricated using standard fabrication techniques.

SUMMARY OF THE INVENTION

[0009] The present invention is directed to a semiconductor structurewhich includes a raised source and a raised drain. The structure alsoincludes a gate located between the source and drains. The gate definesa first gap between the gate and the source and a second gap between thegate and the drain.

[0010] The present invention represents a substantial advance over priorraised source and drain structures. The present invention has theadvantage that it improves the sidewall decoupling of the raisedsource-drain to the polysilicon gate. In one embodiment, the presentinvention also has the advantage that it connects the source and drainto the pocket junction next to the gate edge with a high dose implantfor reduced series resistance. In another embodiment, the presentinvention has the further advantage that the full CMOS process flow isreduced compared to typical raised source-drain CMOS process flows bymaking raised source-drain structures of n+ and p+ polysilicon withrespective pocket junctions by implantation. The present invention alsohas the advantage that conductive source and drain structures can beplaced closer to the polysilicion gate, thereby reducing the size of thestructure. The present invention also has the advantage that implantedareas between the gate and source and drain structures can be fabricatedusing conventional semiconductor processing techniques. The presentinvention has the further advantage that current may move from theimplanted areas to the raised source and drain structures with minimalresistance. Those and other advantages and benefits of the presentinvention will become apparent from the description of the preferredembodiments hereinbelow.

BRIEF DESCRIPTION OF THE DRAWING

[0011] For the present invention to be clearly understood and readilypracticed, the present invention will be described in conjunction withthe following figures, wherein:

[0012]FIG. 1 is a cross-sectional view of a substrate assembly at anearly stage of the fabrication process of the present invention;

[0013]FIG. 2 is a cross-sectional view of the substrate assembly of FIG.1 after portions of the sacrificial layer have been removed;

[0014]FIG. 3 is a cross-sectional view of the substrate assembly of FIG.2 after portions of the oxide layer have been removed;

[0015]FIG. 4 is a cross-sectional view of the substrate assembly of FIG.3 after it has been subject to mechanical abrasion to remove portions ofthe polysilicon layer;

[0016]FIG. 5 is a cross-sectional view of the substrate assembly of FIG.4 after the polysilicon layer has been patterned;

[0017]FIG. 6 is a cross-sectional view of the substrate assembly of FIG.5 after a conductive layer has been formed;

[0018]FIG. 7 is a cross-sectional view of the substrate assembly of FIG.6 after portions of the conductive layer have been removed;

[0019]FIG. 8 is a cross-sectional view of the substrate assembly of FIG.7 after a nonconformal capping layer has been deposited;

[0020]FIG. 9 is a is a cross-sectional view of the substrate assembly ofFIG. 8 after an insulative layer has been deposited and the substrateassembly has been subject to a mechanical abrasion process;

[0021]FIG. 10 is a cross-sectional view of the substrate assembly ofFIG. 9 after contact areas have been patterned and plugs have beenformed;

[0022]FIG. 11 is a cross-sectional view of the substrate assembly ofFIG. 10 after metal layers have been formed and patterned;

[0023]FIG. 12 illustrates a semiconductor device in which the presentinvention may be employed; and

[0024]FIG. 13 is a block diagram illustrating a computer system.

DETAILED DESCRIPTION OF THE INVENTION.

[0025] It is to be understood that the figures and descriptions of thepresent invention have been simplified to illustrate elements andprocess steps that are relevant for a clear understanding of the presentinvention, while eliminating, for purposes of clarity, other elementsand process steps found in a typical semiconductor topography. Forexample, specific methods and steps of removing layers or portions oflayers using techniques such as lithography and etching are notdescribed. Those of ordinary skill in the art will recognize that otherelements and process steps are desirable and/or required to produce anoperational device incorporating the present invention. However, becausesuch elements and process steps are well known in the art, and becausethey do not facilitate a better understanding of the present invention,a discussion of such elements and process steps is not provided herein.

[0026]FIG. 1 is a cross-sectional view of a substrate assembly 10 at anearly stage of the fabrication process of the present invention. Thesubstrate assembly 10 includes a substrate layer 12, which is the lowestlayer of semiconductor material on a wafer, and additional layers orstructures formed thereon. Layers of oxide 14 are formed on thesubstrate layer 12 to create field oxide regions 16 and gate oxideregion 18. The gate oxide region 18 can be, or example, 40 Å thick. Theoxide layers 14 can be formed using any conventional process such as,for example, any form of a shallow trench isolation process or any formof a LOCOS process. A polysilicon layer 20 is formed, typically bydeposition, and patterned using, for example, a lithography and etchprocess to provide a gate terminal of a transistor. The layer 20 canextend over the field to form a terminal for interconnect or may belimited to extending over an active channel area. The formation of thepolysilicon layer 20 may include deposition of polysilicon by a chemicalvapor deposition (CVD) process followed by an ion implantation of adopant, such as phosphorous, to dope the polysilicon layer 20.

[0027] A sacrificial layer 22 is formed on the substrate assembly 10.The sacrificial layer 22 can be any type of dielectric material that isnot difficult to remove using typical semiconductor processingtechniques such as, for example, a thin layer of a nitride, aphotoresist layer, a layer of a polyimide, or a layer of a spin on glass(SOG) material. The sacrificial layer 22 can be deposited by a CVDprocess or by a spin deposition process and if the layer 22 is appliedin a liquid form, it can be baked to form a solid.

[0028]FIG. 2 is a cross-sectional view of the substrate assembly 10 ofFIG. 1 after portions of the sacrificial layer 22 have been removed.Spacers 24 of the sacrificial layer 22 remain after the removal step.The spacers may be rectangular in shape or may have a curved shape.Portions of the sacrificial layer may be removed using a standardremoval technique such as, for example, plasma etching or lithographyand etching.

[0029]FIG. 3 is a cross-sectional view of the substrate assembly 10 ofFIG. 2 after portions of the oxide layers 14 have been removed by aremoval process such as, for example, a lithography and etching process.The field oxide regions 16 and the gate oxide region 18 remain after theremoval step. A polysilicon layer 26 is formed on the substrate assembly10, such as by a CVD process.

[0030]FIG. 4 is a cross-sectional view of the substrate assembly 10 ofFIG. 3 after it has been planarized, such as by mechanical abrasion, toremove portions of the polysilicon layer 26. The mechanical abrasion maybe performed by a technique such as, for example, chemical mechanicalpolishing (CMP). The substrate assembly 10 is substantially planar afterthe planarization.

[0031]FIG. 5 is a cross-sectional view of the substrate assembly 10 ofFIG. 4 after the polysilicon layer 26 has been patterned by, forexample, a lithography and etch process. Raised areas 28 and 30 of thepolysilicon layer 26 may be raised source and drain regions,respectively, of a transistor.

[0032]FIG. 6 is a cross-sectional view of the substrate assembly 10 ofFIG. 5 after a conductive layer 32 is formed. The conductive layer 32acts as a conductive path which carries excess charge built up from theion implantation process off of the wafer, which is connected to anelectrical ground. The conductive layer 32 can be any type of conductorsuitable for use in a semiconductor such as, for example, titaniumsilicide or titanium. The substrate assembly 10 is then masked (notshown) and n+ or p+ dopants are implanted into the polysilicon layer 20and the raised areas 28 and 30 depending on the type of device beingfabricated. The dopants may be, for example, phosphorous, arsenic, orboron atoms.

[0033]FIG. 7 is a cross-sectional view of the substrate assembly 10 ofFIG. 6 after portions of the conductive layer 32 have been removed. Theportions of the conductive layer 32 can be removed by, for example, alithography and etch process. Although certain portions of theconductive layer 32 are shown, the lithography and etch process mayeliminate more or less of the conductive layer 32 than is shown in FIG.7 depending on variations in fabrication processes and depending onwhether a mask is used in the etch process. The amount of the conductivelayer 32 that is removed does not affect the resultant substrateassembly 10. The spacer areas 24 are also removed by a process such asetching to create gaps 34. The gaps 34 may be 100 to 500 Å wide,depending on the height of the polysilicon layer 20 and the raised areas28 and 30. The gaps 34 may be filled with a gas such as, for example,nitrogen, argon, oxygen, or a mixture of such gases (air). A vacuum mayalso be created in the gaps 34.

[0034] The substrate assembly 10 may be masked and blankets of n+ or p+dopants may be implanted, depending on the type of device beingfabricated, beneath the gaps 34 and into the substrate layer 12 tocreate pocket implant junction areas 36, which extend partially underthe polysilicon layer 20 and the raised areas 28 and 30. The areas 36thus create low series resistance paths. The n+ blanket implantdiffluses into the p-channel but is counterdoped by the p+ blanketimplant. The excess dopant thus acts as a p-channel punchthrough haloimplant. The doping process of the polysilicon layer 20 and the raisedareas 28 and 30 as described in conjunction with FIG. 6 createsnegatively doped outdiffusion areas 38. The outdiffusion areas 38 may be50 to 200 Å thick.

[0035] The substrate assembly 10 is subject to a low temperature RTPsinter process. Portions of the conductive layer 32 are converted to anitride by the sinter process. The substrate is then subjected to alithography and etch process to remove some of the nitride in theconductive layer 32. The substrate assembly 10 is then subject to an RTPanneal process. The anneal process causes the conductive layer 32 tobecome more dense and to better adhere to the substrate assembly 10.

[0036]FIG. 8 is a cross-sectional view of the substrate assembly 10 ofFIG. 7 after a nonconformal capping layer 40 has been deposited. Thenonconformal layer 40 can be any type of insulative material suitable toseal the gaps 34 such as, for example, a deposited layer of oxide.

[0037]FIG. 9 is a cross-sectional view of the substrate assembly 10 ofFIG. 8 after an insulative layer 42 has been deposited and the substrateassembly 10 has been subject to a planarization process, such asmechanical abrasion. The mechanical abrasion may be performed by, forexample, chemical mechanical polishing. The substrate assembly 10 issubstantially planar after the planarization. The layer 42 may be amaterial such as doped oxide that is formed by a CVD process. Such dopedoxide may be, for example, phosphosilicate glass (PSG) orborophosphosilicate glass (BPSG).

[0038]FIG. 10 is a cross-sectional view of the substrate assembly 10 ofFIG. 9 after contact areas have been patterned by, for example, alithography and etch process, and plugs 44 have been formed. The plugareas 44 may consist of any type of material suitable such as, forexample, aluminum, copper, or tungsten. An adhesion layer 45 may bedeposited in the contact areas to promote adhesion of the plugs 44 tothe conductive layer 32, the polysilicon layer 20, and the raised areas28 and 30. The adhesion layer may be a material such as, for example,Ti, TiW, TiN, WSi, Ti/TiN, Ti/Cu, Cr/Cu, TiN/Cu, or Ta/Cu.

[0039]FIG. 11 is a cross-sectional view of the substrate assembly 10 ofFIG. 10 after metal layers 46 have been formed and patterned. The metallayers 46 may be constructed of any material suitable for semiconductorinterconnect structures such as, for example, aluminum or copper. Themetal layers may be formed by, for example, a CVD process, byelectroplating, or by electroless plating. Further metal layers may beformed on the substrate assembly 10 to form an interconnect structure.Such metal layers are not illustrated in FIG. 11.

[0040]FIG. 12 illustrates a semiconductor device 48 in which the presentinvention may be employed. The semiconductor device 48 may be any typeof solid state device such as, for example, a memory device.

[0041]FIG. 13 is a block diagram illustrating a computer system 50. Thesystem 50 utilizes a memory controller 52 in communication with RAMs 54through a bus 56. The memory controller 52 is also in communication witha processor 58 through a bus 60. The processor 58 can perform aplurality of functions based on information and data stored in the RAMs54. One or more input devices 62, such as, for example, a keypad or amouse, are connected to the processor 58 to allow an operator tomanually input data, instructions, etc. One or more output devices 64are provided to display or otherwise output data generated by theprocessor 58. Examples of output devices include printers and videodisplay units. One or more data storage devices 66 may be coupled to theprocessor 58 to store data on, or retrieve information from, storagemedia. Examples of storage devices 66 and storage media include drivesthat accept hard and floppy disks, tape cassettes, and CD read onlymemories. The raised source-drain structures of the present inventioncan be incorporated in circuits on all of the devices in the system 50.

[0042] While the present invention has been described in conjunctionwith preferred embodiments thereof, many modifications and variationswill be apparent to those of ordinary skill in the art. The foregoingdescription and the following claims are intended to cover all suchmodifications and variations.

1. A semiconductor structure, comprising: a raised source; a raiseddrain; and a gate located between said source and said drain, said gatedefining a first gap between said gate and said source, and said gatedefining a second gap between said gate and said drain.
 2. The structureof claim 1 wherein said raised source includes doped polysilicon.
 3. Thestructure of claim 1 wherein said raised drain includes dopedpolysilicon.
 4. The structure of claim 1 wherein said gate includesdoped polysilicon.
 5. The structure of claim 1 further comprising acapping layer, said capping layer closing said gaps.
 6. The structure ofclaim 1 further comprising a first junction area located beneath saidfirst gap and a second junction area located beneath said second gap. 7.The structure of claim 1 wherein said first gap is approximately 100 to500 Å wide.
 8. The structure of claim 1 wherein said second gap isapproximately 100 to 500 Å wide.
 9. The structure of claim 1 whereinsaid source includes a plug.
 10. The structure of claim 9 wherein saidplug includes an adhesive layer.
 11. The structure of claim 1 whereinsaid gate includes a gate terminal.
 12. A semiconductor structure formedon a substrate assembly, comprising: a raised source; a raised drain; agate located between said source and said drain, said gate defining afirst gap between said gate and said source, and said gate defining asecond gap between said gate and said drain; a first junction arealocated in the substrate assembly beneath said first gap; and a secondjunction area located in the substrate assembly beneath said second gap.13. The structure of claim 12 wherein said first and second junctionareas include doped silicon areas.
 14. The structure of claim 13 whereinsaid doped silicon areas include phosphorous.
 15. The structure of claim12 wherein said first and said second junctions extend beneath saidgate, said source, and said drain.
 16. The structure of claim 12 whereinsaid first and second junctions include pocket implant junctions.
 17. Atransistor formed on a substrate assembly, comprising: a gate structure;a raised drain structure; a raised source structure; a first junctionarea in the substrate assembly between said gate structure and saidraised drain structure, said first junction area extending beneath saidgate structure and said raised drain structure; and a second junctionarea in the substrate assembly between said gate structure and saidraised source structure, said second junction extending beneath saidgate structure and said raised source structure.
 18. The transistor ofclaim 17 further comprising a capping layer located on the substrateassembly, and wherein said capping layer defines a first capped gaplocated between said gate structure and said raised drain structure andwherein said capping layer defines a second capped gap located betweensaid gate structure and said raised source structure.
 19. The transistorof claim 17 wherein said first and second junctions include doped areas.20. A transistor, comprising: a gate; a raised drain; a raised source;first means for reducing the capacitance between said gate and saidraised drain; and second means for reducing the capacitance between saidgate and said raised source.
 21. The transistor of claim 20 wherein saidfirst means for reducing the capacitance includes a capping layerforming an upper boundary of a gap between said gate and said drain. 22.The transistor of claim 20 wherein said second means for reducing thecapacitance includes a capping layer forming an upper boundary of a gapbetween said gate and said source.
 23. The transistor of claim 20wherein said first means for reducing the capacitance includes a cappedgap.
 24. The transistor of claim 20 wherein said second means forreducing the capacitance includes a capped gap.
 25. The transistor ofclaim 20 further comprising means for providing a conductive pathbetween said gate structure and said raised drain structure.
 26. Thetransistor of claim 25 wherein said means for providing a conductivepath includes a junction.
 27. The transistor of claim 20 furthercomprising means for providing a conductive path between said gatestructure and said raised source structure.
 28. The transistor of claim26 wherein said means for providing a conductive path includes ajunction.
 29. A transistor, comprising: a gate structure; a raised drainstructure; a raised source structure; first means for providing aconductive path between said gate structure and said raised drainstructure; and second means for providing a conductive path between saidgate structure and said raised source structure.
 30. The transistor ofclaim 29 wherein said first and second means for providing a conductivepath include doped areas.
 31. The transistor of claim 29 furthercomprising means for reducing the capacitance between said gatestructure and said raised drain structure.
 32. The transistor of claim29 further comprising means for reducing the capacitance between saidgate structure and said raised source structure.
 33. A semiconductorstructure located on a substrate assembly, comprising: a gate structure;a raised drain structure located adjacent said gate structure, saidraised drain structure defining a gap located between said gatestructure and said raised drain structure; a raised source structurelocated adjacent said gate structure; said raised source structuredefining a gap located between said gate structure and said raisedsource structure; and a capping layer formed on the substrate assembly.34. The structure of claim 33 wherein said capping layer includes aninsulative layer.
 35. The structure of claim 33 wherein said cappinglayer includes an oxide layer.
 36. The structure of claim 33 furthercomprising an insulative layer on the capping layer.
 37. A transistor,comprising: a substrate layer; a gate structure; a first dopedpolysilicon area located adjacent said gate structure, said first dopedpolysilicon area defining a gap located between said gate structure andsaid first doped polysilicon area; a second doped polysilicon arealocated adjacent said gate structure, said second doped polysilicon areadefining a gap located between said gate structure and said second dopedpolysilicon area, a first pocket implant area in said substrate layer,said first implant area located beneath said first doped polysiliconarea; a second pocket implant area in said substrate layer, said secondimplant area located beneath said second doped polysilicon area; and acapping layer, said capping layer closing said gaps.
 38. The transistorof claim 37 wherein said gate structure includes doped polysilicon. 39.The transistor of claim 37 wherein said first doped polysilicon areaincludes a drain structure.
 40. The transistor of claim 37 wherein saidsecond doped polysilicon area includes a source structure.
 41. Thestructure of claim 37 wherein said first and second pocket implant areasinclude phosphorous.
 42. The structure of claim 37 further comprising aninsulative layer above said capping layer.
 43. The structure of claim 37further comprising at least one contact area connected to one of saidgate, said drain, and said source.
 44. The structure of claim 42 furthercomprising at least one metallization layer above said contacts.
 45. Thestructure of claim 44 wherein said metallization layer includesaluminum.
 46. The structure of claim 44 wherein said metallization layerincludes copper.
 47. A method of forming a semiconductor structure on asubstrate assembly, the substrate assembly having a gate, comprising:forming a sacrificial layer on the substrate assembly; removing aportion of said sacrificial layer to form at least one spacer adjacentsaid gate; forming raised source and drains on the substrate assembly;and removing said spacer.
 48. The method of claim 47 wherein forming asacrificial layer includes forming a dielectric layer.
 49. The method ofclaim 47 wherein forming a sacrificial layer includes forming a nitridelayer.
 50. The method of claim 47 wherein forming a sacrificial layerincludes depositing a nitride layer.
 51. The method of claim 47 whereinforming a sacrificial layer includes forming a photoresist layer. 52.The method of claim 47 wherein forming a sacrificial layer includesforming a polyimide layer.
 53. The method of claim 47 wherein forming asacrificial layer includes forming an SOG layer.
 54. The method of claim47 wherein removing a portion of said sacrificial layer includes etchingsaid sacrificial layer.
 55. The method of claim 47 wherein formingraised source and drains includes forming polysilicon areas.
 56. Themethod of claim 55 wherein forming raised source and drains includesetching said polysilicon areas.
 57. The method of claim 56 whereinforming raised source and drains includes doping said etched polysiliconareas.
 58. The method of claim 57 wherein forming raised source anddrains includes doping said etched polysilicon with phosphorous.
 59. Themethod of claim 47 wherein removing said spacer includes etching saidspacer.
 60. The method of claim 47 further comprising forming a cappinglayer on the substrate assembly.
 61. A method of forming a semiconductorstructure with a gate on a substrate assembly, comprising: forming asacrificial layer on the substrate assembly; removing a portion of saidsacrificial layer to form at least one spacer adjacent said gate;forming raised source and drains on the substrate assembly; removingsaid spacer; and forming a capping layer on the substrate assembly. 62.The method of claim 61 wherein forming a capping layer includes formingan insulative layer.
 63. The method of claim 61 wherein forming acapping layer includes forming an oxide layer.
 64. The method of claim61 wherein forming a capping layer includes depositing an oxide layer.65. The method of claim 61 further comprising forming an insulativelayer on the substrate assembly.
 66. The method of claim 61 furthercomprising forming a doped oxide insulative layer on the substrateassembly.
 67. A method of forming a semiconductor structure with a gateon a substrate assembly, comprising: forming a sacrificial layer on thesubstrate assembly; removing a portion of said sacrificial layer to format least one spacer adjacent said gate; forming raised source and drainson said substrate assembly; removing said spacer to form a gap; andforming a junction area beneath said gap and partially beneath saidgate.
 68. The method of claim 67 wherein forming a junction areaincludes implanting dopants beneath said gap and partially beneath saidgate and one of said raised source and drains.
 69. The method of claim67 wherein forming a junction area includes implanting phosphorousbeneath said gap and partially beneath said gate and one of said raisedsource and drains.
 70. The method of claim 67 wherein forming a junctionarea includes forming a conductive layer on the substrate assembly. 71.The method of claim 67 wherein forming a junction area includes formingan outdiffusion area.
 72. The method of claim 67 wherein forming ajunction area includes implanting dopants.
 73. The method of claim 67wherein forming a junction area includes forming a shallow lightly dopedarea.
 74. A method of forming a semiconductor structure having a gate ona substrate assembly, comprising: forming a sacrificial layer on thesubstrate assembly; removing a portion of said sacrificial layer to format least one spacer adjacent said gate; forming raised source and drainson said substrate assembly; removing said spacer to form a gap; forminga junction area substantially beneath said gap; and forming a cappinglayer on the substrate assembly.
 75. A method of forming a semiconductorstructure with raised source and drains on a substrate assembly, thesubstrate assembly having a gate, comprising: forming a gap between thesource and the gate; and forming a pocket implant beneath said gap andpartially beneath the gate and the raised source.
 76. The method ofclaim 75 wherein forming a pocket implant includes forming anoutdiffusion area beneath the raised source.
 77. A method of forming asemiconductor structure with raised source and drains on a substrateassembly, the substrate assembly having a gate, comprising: forming agap between the drain and the gate; and forming a pocket implantsubstantially beneath said gap and partially beneath the gate and theraised drain.
 78. The method of claim 77 wherein forming a pocketimplant includes forming an outdiffusion area beneath the raised drain.79. A method of creating a transistor on a substrate assembly,comprising: forming a gate structure; forming raised source and drainstructures; and forming junction areas in the substrate assembly betweensaid gate structure and said raised source structure and between saidgate structure and said raised drain structure, said junction areasextending beneath said gate structure and said raised source and drains.80. The method of claim 79 wherein forming a gate structure includesforming a doped polysilicon layer on the substrate assembly.
 81. Themethod of claim 80 wherein forming a layer of doped polysilicon includeschemically vapor depositing a polysilicon layer and doping saidpolysilicon layer with phosphorous.
 82. A method of forming a transistoron a substrate assembly, comprising: forming an oxide layer on asubstrate layer; forming a doped polysilicon layer on said oxide layer;removing portions of said doped polysilicon layer to form a gate;forming a sacrificial layer on the substrate assembly; removing portionsof said sacrificial layer to form a plurality of spacers adjacent saidgate; removing portions of said oxide layer; forming a polysilicon layeron the substrate assembly; planarizing said substrate assembly; removingportions of said polysilicon layer to form a raised source and a raiseddrain; forming a conductive layer on the substrate assembly; doping saidpolysilicon layer; removing portions of said conductive layer; removingsaid spacers to create a plurality of gaps; doping said substrate layerbeneath said gaps; forming a capping layer on said substrate assembly;and forming an insulative layer on said substrate assembly.
 83. Themethod of claim 82 wherein forming a conductive layer includesdepositing a titanium layer.
 84. The method of claim 82 wherein formingan insulative layer includes forming a PSG layer.
 85. The method ofclaim 82 wherein forming an insulative layer includes forming a BPSGlayer.
 86. The method of claim 82 further comprising planarizing thesubstrate assembly after forming an insulative layer.
 87. The method ofclaim 82 further comprising forming contact areas on the substrateassembly after forming said insulative layer.
 88. The method of claim 87further comprising forming an adhesion layer on the substrate assemblyafter forming contact areas.
 89. The method of claim 82 furthercomprising forming at least one metallization layer on said substrateassembly after forming said insulative layer.
 90. The method of claim 89wherein forming at least one metallization layer includes forming atleast one aluminum layer.
 91. The method of claim 89 wherein forming atleast one metallization layer includes forming at least one copperlayer.
 92. The method of claim 82 further comprising RTP sintering thesubstrate assembly after doping said substrate layer substantiallybeneath said gaps.
 93. The method of claim 92 further comprising RTPannealing the substrate assembly after RTP sintering the substrateassembly.
 94. A semiconductor device, comprising: a substrate assembly;at least one raised source; at least one raised drain; and at least onegate located between said source and said drain, said gate defining afirst gap between said gate and said source, and said gate defining asecond gap between said gate and said drain.
 95. A semiconductor device,comprising: a substrate assembly; at least one raised source; at leastone raised drain; at least one gate located between said source and saiddrain, said gate defining a first gap between said gate and said source,and said gate defining a second gap between said gate and said drain; afirst junction area located in said substrate assembly beneath saidfirst gap; and a second junction area located in said substrate assemblybeneath said second gap.
 96. A system, comprising: a memory devicehaving at least one semiconductor structure, said structure including: araised source; a raised drain; and a gate located between said sourceand said drain, said gate defining a first gap between said gate andsaid source, and said gate defining a second gap between said gate andsaid drain; a processor; and a bus connecting said processor and saidmemory device.
 97. A system, comprising: a memory device having at leastone semiconductor structure formed on a substrate assembly, saidstructure including: a raised source; a raised drain; a gate locatedbetween said source and said drain, said gate defining a first gapbetween said gate and said source, and said gate defining a second gapbetween said gate and said drain; a first junction area located in thesubstrate assembly beneath said first gap; and a second junction arealocated in the substrate assembly beneath said second gap; a processor;and a bus connecting said processor and said memory device.